Will Killian
2019 Fall
CSCI 370
Information
Syllabus
Resources
Labs
CSCI 420
Information
Syllabus
Resources
CSCI 370: Final Review
Instruction Level Parallelism
Loop Unrolling
Sequential vs Parallel computation
Functional efficiencies
Code Optimization
Static Analysis
Alias, Pointer, Shape, Escape, Array Access, Dependence, Control Flow, Data Flow
Be able to describe TWO
Intermediate Representation
What is it?
Why is it useful?
Memory Hierarchy
DRAM Structure / Access pattern (RAS, CAS, cell, supercell)
Bus structure
{ CPU } <==( system bus )==> { I/O bridge } <==( memory bus )==> { memory }
Memory read vs write
Principles of Locality
Temporal vs Spatial
Example Hierarchy (registers, L1, L2, L3, Memory, Storage)
Caches
Definition
Terms: cacheline, set, associativity, offset, block size
Hits vs Misses
Compulsory vs Capacity vs Conflict (misses)
Direct vs K-way associative vs Fully associative
Simulating a sequence of memory accesses
Miss rate + miss penalty
Cache Performance
Memory Mountain (analyze a picture / compare two figures)
loop transformations (permutation, blocking)
Virtual Memory
Definition
Terms: Physical vs Virtual Address, Page Table, Page Fault
Translation Lookaside Buffer (TLB) -- what is it? how does it work?
Mapping from VA to PA -- steps taken
Simulating memory accesses with TLB, configuration, and Page Table
Multi-level page tables -- justification?
Exceptions
definition
synchronous vs asynchronous
interrupt vs trap vs fault vs abort
Linking
Types of Object files
Why use linkers?
What do linkers do?
ELF Binary: .text, .data, .bss, .rodata
Global vs External vs Local symbols
Strong vs Weak symbols
x87 and SIMD:
x87 stack-based example
definition of SIMD
SSE registers + instruction naming conventions
packed vs scalar
float vs double
Virtualization and System IO
gang scheduling vs hypervisors
USB / Thunderbolt: trends over time
PCIe: trends over time; how is data transferred
Multicore
Snoopy cache (dirty bit)
False sharing
Hyperthreading vs Multicore
what is replicated?
what isn't replicated?
Low Power
ARM ISA
Barrel Shifter
Instruction Format
conditional execution
setting condition codes